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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. 16-bit microcontroller with infrared module maxq61c 19-5231; rev 0; 4/10 ordering information/selector guide general description the maxq61c is a low-power, 16-bit maxq ? micro - controller designed for low-power applications including universal remote controls, consumer electronics, and white goods. the device combines a powerful 16-bit risc microcontroller and integrated peripherals includ - ing two universal synchronous/asynchronous receiver- transmitters (usarts) and an spi? master/slave com - munications port, along with an ir module with carrier frequency generation and flexible port i/o capable of multiplexed keypad control. the device includes 80kb of rom memory and 2kb of data sram. for the ultimate in low-power battery-operated perfor - mance, the device includes an ultra-low-power stop mode (0.2a typ). in this mode, the minimum amount of circuitry is powered. wake-up sources include external interrupts, the power-fail interrupt, and a timer interrupt. the microcontroller runs from a wide 1.70v to 3.6v oper - ating voltage. applications remote controls battery-powered portable equipment consumer electronics home appliances white goods features s high-performance, low-power, 16-bit risc core s dc to 12mhz operation across entire operating range s 1.70v to 3.6v operating voltage s 33 total instructions for simplified programming s three independent data pointers accelerate data movement with automatic increment/decrement s dedicated pointer for direct read from code space s 16-bit instruction word, 16-bit data bus s 16 x 16-bit general-purpose working registers s memory features 80kb application rom 2kb data sram s additional peripherals power-fail warning power-on reset (por)/brownout reset automatic ir carrier frequency generation and modulation two 16-bit programmable timers/counters with prescaler and capture/compare one spi port and two usart ports programmable watchdog timer 8khz nanopower ring oscillator wake-up timer up to 32 general-purpose i/os (j, k, and x versions only) s low power consumption 0.2a (typ), 2.0a (max) in stop mode, t a = +25 n c, power-fail monitor disabled 2.0ma (typ) at 12mhz in active mode note: contact the factory for information about masked rom devices. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. maxq is a registered trademark of maxim integrated products, inc. spi is a trademark of motorola, inc. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . part temp range operating voltage (v) program memory (kb) data memory (kb) gpio pin-package maxq61ca-xxxx+ 0 n c to +70 n c 1.7 to 3.6 80 rom 2 20 32 tqfn-ep* maxq61ce-xxxx+ 0 n c to +70 n c 1.7 to 3.6 80 rom 2 20 32 lqfp maxq61cj-xxxx+ 0 n c to +70 n c 1.7 to 3.6 80 rom 2 32 44 tqfn-ep* MAXQ61CK-xxxx+ 0 n c to +70 n c 1.7 to 3.6 80 rom 2 32 44 tqfp maxq61cx-xxxx+ 0 n c to +70 n c 1.7 to 3.6 80 rom 2 32 bare die
16-bit microcontroller with infrared module maxq61c 2 ______________________________________________________________________________________ table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 spi electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 stack memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 utility rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ir carrier generation and modulation timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 carrier generation module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ir transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ir transmitindependent external carrier and modulator outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ir receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 carrier burst-count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 16-bit timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 power-fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 grounds and bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 additional documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 deviations from the maxq610 users guide for the maxq61c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 development and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16-bit microcontroller with infrared module maxq61c _______________________________________________________________________________________ 3 list of figures figure 1. ir transmit frequency shifting example (ircfme = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2. ir transmit carrier generation and carrier modulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. ir transmission waveform (ircfme = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. external irtxm (modulator) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. ir capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. receive burst-count example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. spi master communication timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. spi slave communication timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. power-fail detection during normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. stop mode power-fail detection states with power-fail monitor enabled . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. stop mode power-fail detection with power-fail monitor disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 list of tables table 1. watchdog interrupt timeout (sysclk = 12mhz, cd[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. usart mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3. power-fail detection states during normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. stop mode power-fail detection states with power-fail monitor enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. stop mode power-fail detection states with power-fail monitor disabled . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16-bit microcontroller with infrared module maxq61c 4 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v dd with respect to gnd ..... -0.3v to +3.6v voltage range on any lead with respect to gnd except v dd ............... -0.3v to (v dd + 0.5v) continuous power dissipation (t a = +70 n c) 32-pin tqfn (single-layer board) (derate 21.3mw/ n c above +70 n c) .......................... 1702.1mw 32-pin tqfn (multilayer board) (derate 34.5mw/ n c above +70 n c) .......................... 2758.6mw 32-pin lqfp (multilayer board) (derate 20.7mw/ n c above +70 n c) .......................... 1652.9mw 44-pin tqfn (single-layer board) (derate 27mw/ n c above +70 n c) ............................. 2162.2mw 44-pin tqfn (multilayer board) (derate 37mw/ n c above +70 n c) ................................ 2963mw operating temperature range ............................. 0 n c to +70 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (excluding dice; soldering, 10s) ...... +300 n c soldering temperature (reflow) ...................................... +260 n c recommended operating conditions (v dd = v rst to 3.6v, t a = 0 n c to +70 n c, unless otherwise noted.) (note 1) absolute maximum ratings parameter symbol conditions min typ max units supply voltage v dd v rst 3.6 v 1.8v internal regulator v reg18 1.62 1.8 1.98 v power-fail warning voltage for supply v pfw monitors v dd 1.75 1.8 1.85 v power-fail reset voltage v rst monitors v dd (note 2) 1.64 1.67 1.70 v por voltage v por monitors v dd 1.0 1.42 v ram data-retention voltage v drv (note 3) 1.0 v active current i dd_1 sysclk = 12mhz (note 4) 2.5 3.75 ma stop-mode current i s1 power-fail off t a = +25 n c 0.15 2.0 f a t a = 0 c +70 n c 0.15 8 i s2 power-fail on t a = +25 n c 22 31 t a = 0 c to +70 n c 27.6 38 current consumption during power-fail i pfr (note 5) [(3 x i s2 ) + ((pci - 3) x (i s1 + i nano ))]/pci f a power consumption during por i por (note 6) 100 na stop-mode resume time t on 375 + (8192 x t hfxin) f s power-fail monitor startup time t pfm_on (note 3) 150 f s power-fail warning detection time t pfw (notes 3, 7) 10 f s input low voltage for irtx, irrx, reset , and all port pins v il v gnd 0.3 x v dd v input high voltage for irtx, irrx, reset , and all port pins v ih 0.7 x v dd v dd v input hysteresis (schmitt) v ihys v dd = 3.3v, t a = +25 n c 300 mv input low voltage for hfxin v il_hfxin v gnd 0.3 x v dd v input high voltage for hfxin v ih_hfxin 0.7 x v dd v dd v
16-bit microcontroller with infrared module maxq61c _______________________________________________________________________________________ 5 recommended operating conditions (continued) (v dd = v rst to 3.6v, t a = 0 n c to +70 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units irrx input filter pulse-width reject t irrx_r 50 ns irrx input filter pulse-width accept t irrx_a 300 ns output low voltage for irtx v ol_irtx v dd = 3.6v, i ol = 25ma (note 3) 1.0 v v dd = 2.35v, i ol = 10ma (note 3) 1.0 v dd = 1.85v, i ol = 4.5ma 1.0 output low voltage for reset and all port pins (note 8) v ol v dd = 3.6v, i ol = 11ma (note 3) 0.4 0.5 v v dd = 2.35v, i ol = 8ma (note 3) 0.4 0.5 v dd = 1.85v, i ol = 4.5ma 0.4 0.5 output high voltage for irtx and all port pins v oh i oh = -2ma v dd - 0.5 v dd v input/output pin capacitance for all port pins c io (note 3) 15 pf input leakage current i l internal pullup disabled -100 +100 na input pullup resistor for reset , irtx, irrx, p0, p1, p2 r pu v dd = 3.0v, v ol = 0.4v (note 3) 16 28 39 k w v dd = 2.0v, v ol = 0.4v 17 30 41 external crystal/resonator crystal/resonator f hfxin dc 12 mhz crystal/resonator period t hfxin 1/f hfxin ns crystal/resonator warmup time t xtal_rdy from initial oscillation 8192 x t hfxin ms oscillator feedback resistor r oscf (note 3) 0.5 1.0 1.5 m w external clock input external clock frequency f xclk dc 12 mhz external clock period t xclk 1/f xclk ns external clock duty cycle t xclk_duty (note 3) 45 55 % system clock frequency f ck f hfxin mhz hfxout = gnd f xclk system clock period t ck 1/f ck ns nanopower ring nanopower ring frequency f nano t a = +25 n c 3.0 8.0 20.0 khz t a = +25 n c, v dd = por voltage (note 3) 1.7 2.4 nanopower ring duty cycle t nano (note 3) 40 60 % nanopower ring current i nano typical at v dd = 1.64v, t a = +25 c (note 3) 40 400 na wake-up timer wake-up timer interval t wakeup 1/f nano 65,535/ f nano s ir carrier frequency f ir (note 3) f ck /2 hz
16-bit microcontroller with infrared module maxq61c 6 ______________________________________________________________________________________ spi electrical characteristics (v dd = v rst to 3.6v, t a = 0 n c to +70 n c, unless otherwise noted.) (note 9) note 1: specifications to 0 n c are guaranteed by design and are not production tested. typical = +25 n c, v dd = +3.3v, unless otherwise noted. note 2: the power-fail reset and por detectors are designed to operate in tandem to ensure that one or both of these signals is active at all times when v dd < v rst , ensuring the device maintains the reset state until minimum operating voltage is achieved. note 3: guaranteed by design and not production tested. note 4: measured on the v dd pin and the device not in reset. all inputs are connected to gnd or v dd . outputs do not source/ sink any current. the device is executing code from rom memory. note 5: the power-check interval (pci) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles. note 6: current consumption during por when powering up while v dd is less than the por release voltage. note 7: the minimum amount of time that v dd must be below v pfw before a power-fail event is detected; refer to the maxq610 users guide for details. note 8: the maximum total current, i oh(max) and i ol(max) , for all listed outputs combined should not exceed 32ma to satisfy the maximum specified voltage drop. this does not include the irtx output. note 9: ac electrical specifications are guaranteed by design and are not production tested. parameter symbol conditions min typ max units spi master operating frequency 1/t mck f ck /2 mhz spi slave operating frequency 1/t sck f ck /4 mhz spi i/o rise/fall time t spi_rf c l = 15pf, pullup = 560 w 8.3 23.6 ns sclk output pulse-width high/ low t mch , t mcl t mck /2 - t spi_rf ns mosi output hold time after sclk sample edge t moh t mck /2 - t spi_rf ns mosi output valid to sample edge t mov t mck /2 - t spi_rf ns miso input valid to sclk sample edge rise/fall setup t mis 25 ns miso input to sclk sample edge rise/fall hold t mih 0 ns sclk inactive to mosi inactive t mlh t mck /2 - t spi_rf ns sclk input pulse-width high/low t sch , t scl t sck /2 ns ssel active to first shift edge t sse t spi_rf ns mosi input to sclk sample edge rise/fall setup t sis t spi_rf ns mosi input from sclk sample edge transition hold t sih t spi_rf ns miso output valid after sclk shift edge transition t sov 2t spi_rf ns ssel inactive t ssh t ck + t spi_rf ns sclk inactive to ssel rising t sd t spi_rf ns miso output disabled after ssel edge rise t slh 2t ck + 2t spi_rf ns
16-bit microcontroller with infrared module maxq61c _______________________________________________________________________________________ 7 pin configurations tqfn (5mm 5mm) top view 29 30 28 27 12 11 13 p0.1/rx0 p0.3/rx1 p0.4/tx1 p0.5/tba0/tba1 p0.6/tbb0 14 p0.0/irtxm p1.1/int1 p2.7/tdo p2.6/tms p1.2/int2 p2.5/tdi p2.4/tck 1 2 p1.6/int6 4 5 6 7 23 24 22 20 19 18 p1.7/int7 gnd hfxout hfxin gnd regout p0.2/tx0 p1.0/int0 3 + 21 31 10 irtx ep v dd 32 9 irrx reset p1.5/int5 26 15 n.c. p1.4/int4 25 16 n.c. p0.7/tbb1 gnd 8 17 p1.3/int3 maxq61c lqfp (7mm 7mm) top view 29 30 28 27 12 11 13 p0.1/rx0 p0.3/rx1 p0.4/tx1 p0.5/tba0/tba1 p0.6/tbb0 14 p0.0/irtxm p1.1/int1 p2.7/tdo p2.6/tms p1.2/int2 p2.5/tdi p2.4/tck 1 2 p1.6/int6 4 5 6 7 23 24 22 20 19 18 p1.7/int7 gnd hfxout hfxin gnd regout p0.2/tx0 p1.0/int0 3 21 31 10 irtx v dd 32 9 irrx reset reset p1.5/int5 26 15 n.c. p1.4/int4 25 16 n.c. p0.7/tbb1 gnd 8 17 p1.3/int3 maxq61c + p0.3/rx1 p0.4/tx1 p0.5/tba0/tba1 p0.6/tbb0 p0.7/tbb1 p2.0/mosi p2.1/miso p2.2/sclk p0.2/tx0 p0.1/rx0 1 2 3 4 5 6 7 8 9 10 11 p1.3/int3 p1.4/int4 p1.5/int5 p1.6/int6 p1.7/int7 gnd irtx irrx p0.0/irtxm p1.2/int2 p1.1/int1 34 35 36 37 38 39 40 41 42 43 44 p3.2/int10 p3.1/int9 p3.0/int8 hfxout hfxin gnd regout v dd p3.3/int11 p3.4/int12 22 21 20 19 18 17 16 15 14 13 12 p2.6/tms p2.5/tdi p2.4/tck gnd n.c. n.c. p3.7/int15 p3.6/int14 p3.5/int13 p2.7/tdo p1.0/int0 33 32 31 30 29 28 27 26 25 24 23 tqfn (7mm 7mm) top view + ep maxq61c p2.3/ssel
16-bit microcontroller with infrared module maxq61c 8 ______________________________________________________________________________________ pin configurations (continued) tqfp (10mm 10mm) top view 12 13 v dd 14 regout 15 gnd 16 hfxin 17 hfxout 18 p3.0/int8 19 p3.1/int9 20 p3.2/int10 21 p3.3/int11 22 p3.4/int12 p1.0/int0 33 p3.6/int14 24 p3.5/int13 23 p3.7/int15 25 n.c. 26 n.c. 27 gnd 28 p2.4/tck 29 p2.5/tdi 30 p2.6/tms 31 p2.7/tdo 32 p0.1/rx0 1 p0.2/tx0 2 p0.3/rx1 3 p0.4/tx1 4 p0.5/tba0/tba1 5 p0.6/tbb0 6 p0.7/tbb1 7 p2.0/mosi 8 p2.1/miso 9 11 p2.2/sclk 10 34 p1.1/int1 44 p0.0/irtxm 43 irrx note: contact factory for bare die pad configuration. 42 irtx 41 gnd 40 p1.7/int7 39 p1.6/int6 38 p1.5/int5 37 p1.4/int4 36 p1.3/int3 35 p1.2/int2 maxq61c + p2.3/ssel reset
16-bit microcontroller with infrared module maxq61c _______________________________________________________________________________________ 9 pin description pin name function bare die 32 tqfn- ep/lqfp 44 tqfn- ep/tqfp power pins 14 10 13 v dd supply voltage 16 12 15 gnd ground. connect directly to the ground plane. 27, 40 17, 30 28, 41 gnd ground. for low-current applications (< 10ma of gpio current, exclu - sive of irtx sink current), these pins can be left unconnected. if used, they should be connected directly to the ground plane. 15 11 14 regout 1.8v regulator output. this pin must be connected to ground through a 1.0 f f (esr: 2C10 w ) external ceramic-chip capacitor. the capacitor must be placed as close to this pin as possible. no devices other than the capacitor should be connected to this pin. ep exposed pad (tqfn only). for low-current applications (< 10ma of gpio current, exclusive of irtx sink current), these pins can be left unconnected. if used, they should be connected directly to the ground plane. reset pins 13 9 12 reset digital, active-low reset input/output. the device remains in reset as long as this pin is low and begins executing from the utility rom at address 8000h when this pin returns to a high state. the pin includes pullup current source; if this pin is driven by an external device, it should be driven by an open-drain source capable of sinking in excess of 4ma. this pin can be left unconnected if there is no need to place the device in a reset state using an external signal. this pin is driven low as an output when an internal reset condition occurs. clock pins 17 13 16 hfxin high-frequency crystal input. connect an external crystal or resona - tor between hfxin and hfxout for use as the high-frequency system clock. alternatively, hfxin is the input for an external, high-frequency clock source when hfxout is connected to ground. 18 14 17 hfxout ir function pins 41 31 42 irtx ir transmit output. ir transmission pin capable of sinking 25ma. this pin defaults to a high-impedance input with the weak pullup disabled during all forms of reset. software must configure this pin after release from reset to remove the high-impedance input condition. 42 32 43 irrx ir receive input. this pin defaults to a high-impedance input with the weak pullup disabled during all forms of reset. software must configure this pin after release from reset to remove the high-impedance input condition.
16-bit microcontroller with infrared module maxq61c 10 _____________________________________________________________________________________ pin description (continued) pin name function bare die 32 tqfn- ep/lqfp 44 tqfn- ep/tqfp general-purpose i/o and special function pins port 0 general-purpose, digital i/o pins. these port pins function as general-purpose i/o pins with their input and output states controlled by the pd0, po0, and pi0 registers. all port pins default to high-impedance mode after a reset. software must configure these pins after release from reset to remove the high-impedance condition. all special func - tions must be enabled from software before they can be used. gpio port pin special function 1 1 44 p0.0/irtxm p0.0 ir modulator output 2 2 1 p0.1/rx0 p0.1 usart 0 receive 3 3 2 p0.2/tx0 p0.2 usart 0 transmit 4 4 3 p0.3/rx1 p0.3 usart 1 receive 5 5 4 p0.4/tx1 p0.4 usart 1 transmit 6 6 5 p0.5/tba0/ tba1 p0.5 type b timer 0 pin a or type b timer 1 pin a 7 7 6 p0.6/tbb0 p0.6 type b timer 0 pin b 8 8 7 p0.7/tbb1 p0.7 type b timer 1 pin b port 1 general-purpose, digital i/o pins with interrupt capability. these port pins function as general-purpose i/o pins with their input and out - put states controlled by the pd1, po1, and pi1 registers. all port pins default to high-impedance mode after a reset. software must configure these pins after release from reset to remove the high-impedance con - dition. all external interrupts must be enabled from software before they can be used. gpio port pin external interrupt 32 22 33 p1.0/int0 p1.0 int0 33 23 34 p1.1/int1 p1.1 int1 34 24 35 p1.2/int2 p1.2 int2 35 25 36 p1.3/int3 p1.3 int3 36 26 37 p1.4/int4 p1.4 int4 37 27 38 p1.5/int5 p1.5 int5 38 28 39 p1.6/int6 p1.6 int6 39 29 40 p1.7/int7 p1.7 int7
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 11 pin description (continued) pin name function bare die 32 tqfn- ep/lqfp 44 tqfn- ep/tqfp port 2 general-purpose, digital i/o pins. these port pins function as general-purpose i/o pins with their input and output states controlled by the pd2, po2, and pi2 registers. all port pins default to high-impedance mode after a reset. software must configure these pins after release from reset to remove the high-impedance condition. all special func - tions must be enabled from software before they can be used. gpio port pin special function 9 8 p2.0/mosi p2.0 spi: master out-slave in 10 9 p2.1/miso p2.1 spi: master in-slave out 11 10 p2.2/sclk p2.2 spi: slave clock 12 11 p2.3/ ssel p2.3 spi: active-low slave select 28 18 29 p2.4/tck p2.4 jtag: test clock 29 19 30 p2.5/tdi p2.5 jtag: test data in 30 20 31 p2.6/tms p2.6 jtag: test mode select 31 21 32 p2.7/tdo p2.7 jtag: test data out port 3 general-purpose, digital i/o pins with interrupt capability. these port pins function as general-purpose i/o pins with their input and out - put states controlled by the pd3, po3, and pi3 registers. all port pins default to high-impedance mode after a reset. software must configure these pins after release from reset to remove the high-impedance con - dition. all external interrupts must be enabled from software before they can be used. gpio port pin external interrupt 19 18 p3.0/int8 p3.0 int8 20 19 p3.1/int9 p3.1 int9 21 20 p3.2/int10 p3.2 int10 22 21 p3.3/int11 p3.3 int11 23 22 p3.4/int12 p3.4 int12 24 23 p3.5/int13 p3.5 int13 25 24 p3.6/int14 p3.6 int14 26 25 p3.7/int15 p3.7 int15 no connection pins 15, 16 26, 27 n.c. no connection. not internally connected.
16-bit microcontroller with infrared module maxq61c 12 _____________________________________________________________________________________ detailed description the maxq61c provides integrated, low-cost solutions that simplify the design of ir communications equip - ment such as universal remote controls. standard fea - tures include the highly optimized, single-cycle, maxq, 16-bit risc core; 80kb of user rom memory; 2kb data ram; soft stack; 16 general-purpose registers; and three data pointers. the maxq core has the industrys best mips/ma rating, allowing developers to achieve the same performance as competing microcontrollers at substantially lower clock rates. lower active-mode current combined with the even lower maxq61c stop- mode current (0.2 f a typ) results in increased battery life. application-specific peripherals include flexible timers for generating ir carrier frequencies and modula - tion. a high-current ir drive pin capable of sinking up to 25ma current and output pins capable of sinking up to 5ma are ideal for ir applications. it also includes gen - eral-purpose i/o pins ideal for keypad matrix input, and a power-fail-detection circuit to notify the application when the supply voltage is nearing the microcontrollers minimum operating voltage. at the heart of the device is the maxq 16-bit, risc core. operating from dc to 12mhz, almost all instructions exe - cute in a single clock cycle (83.3ns at 12mhz), enabling nearly 12mips true-code operation. when active device operation is not required, an ultra-low-power stop mode can be invoked from software, resulting in quiescent current consumption of less than 0.2 f a (typ) and 2.0 f a (max). the combination of high-performance instructions and ultra-low stop-mode current increases battery life over competing microcontrollers. an integrated por cir - cuit with brownout support resets the device to a known condition following a power-up cycle or brownout condi - tion. additionally, a power-fail warning flag is set, and a power-fail interrupt can be generated when the system voltage falls below the power-fail warning voltage, v pfw . the power-fail warning feature allows the application to notify the user that the system supply is low and appro - priate action should be taken. microprocessor the device is based on maxims low-power, 16-bit maxq family of risc cores. the core supports the harvard memory architecture with separate 16-bit program and data address buses. a fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. the maxq core in the device is implemented as a pipe - lined processor with performance approaching 1mips per mhz. the 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. the accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (alu). a configurable soft stack supports program flow. execution of instructions is triggered by data transfer between functional register modules or between a func - tional register module and memory. because data move - ment involves only source and destination modules, circuit switching activities are limited to active modules only. for power-conscious applications, this approach localizes power dissipation and minimizes switching noise. the modular architecture also provides a maxi - mum of flexibility and reusability that are important for a microprocessor used in embedded applications. the maxq instruction set is highly orthogonal. all arith - metical and logical operations can use any register in conjunction with the accumulator. data movement is supported from any register to any other register. memory is accessed through specific data-pointer reg - isters with autoincrement/decrement support. memory the microcontroller incorporates several memory types: ? 80kb user rom ? 2kb sram data memory ? 1.5kb utility rom ? soft stack block diagram 16-bit maxq risc cpu 2kb data sram usart x2 8khz nano ring 2x 16-bit timer gpio voltage monitor clock 80kb user rom ir timer watchdog 1.5kb utility rom spi ir driver regulator maxq61c
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 13 stack memory the device provides a soft stack that can be used to store program return addresses (for subroutine calls and interrupt handling) and other general-purpose data. this soft stack is located in the 2kb sram data mem - ory, which means that the sram data memory must be shared between the soft stack and general-purpose application data storage. however, the location and size of the soft stack is determined by the user, provid - ing maximum flexibility when allocating resources for a particular application. the stack is used automatically by the processor when the call, ret, and reti instruc - tions are executed and when an interrupt is serviced. an application can also store and retrieve values explicitly using the stack by means of the push, pop, and popi instructions. the sp pointer indicates the current top of the stack, which initializes by default to the top of the sram data memory. as values are pushed onto the stack, the sp pointer decrements, which means that the stack grows downward towards the bottom (lowest address) of the data memory. popping values off the stack causes the sp pointer value to increase. refer to the maxq610 users guide for more details. utility rom the utility rom is a 1.5kb block of internal rom memory located in program space beginning at address 8000h. this rom includes the following routines: ? production test routines (internal memory tests, memory loader, etc.), which are used for internal testing only, and are generally of no use to the end- application developer ? user-callable routines for buffer copying and fast table lookup (more information on these routines can be found in the maxq610 users guide) following any reset, execution begins in the utility rom at address 8000h. at this point, unless test mode has been invoked (which requires special programming through the jtag interface), the utility rom in the device always automatically jumps to location 0000h, which is the beginning of user application code. watchdog timer the internal watchdog timer greatly increases system reliability. the timer resets the device if software execu - tion is disturbed. the watchdog timer is a free-running counter designed to be periodically reset by the applica - tion software. if software is operating correctly, the coun - ter is periodically reset and never reaches its maximum count. however, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. this protects the system against electrical noise or electrostatic discharge (esd) upsets that could cause uncontrolled processor operation. the internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. the watchdog timer functions as the source of both the watchdog timer timeout and the watchdog timer reset. the timeout period can be programmed in a range of 2 15 to 2 24 system clock cycles. an interrupt is gener - ated when the timeout period expires if the interrupt is enabled. all watchdog timer resets follow the pro - grammed interrupt timeouts by 512 system clock cycles. if the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. see table 1. ir carrier generation and modulation timer the dedicated ir timer/counter module simplifies low- speed infrared (ir) communication. the ir timer imple - ments two pins (irtx and irrx) for supporting ir transmit and receive, respectively. the irtx pin has no corresponding port pin designation, so the standard pd, po, and pi port control status bits are not present. however, the irtx pin output can be manipulated high or low using the pwcn.irtxout and pwcn.irtxoe bits when the ir timer is not enabled (i.e., iren = 0). table 1. watchdog interrupt timeout (sysclk = 12mhz, cd[1:0] = 00) wd[1:0] watchdog clock watchdog interrupt timeout watchdog reset after watchdog interrupt ( s) 00 sysclk/2 15 2.7ms 42.7 01 sysclk/2 18 21.9ms 42.7 10 sysclk/2 21 174.7ms 42.7 11 sysclk/2 24 1.4s 42.7
16-bit microcontroller with infrared module maxq61c 14 _____________________________________________________________________________________ the ir timer is composed of a carrier generator and a carrier modulator. the carrier generation module uses the 16-bit ir carrier register (irca) to define the high and low time of the carrier through the ir carrier high byte (ircah) and ir carrier low byte (ircal). the carrier modulator uses the ir data bit (irdata) and ir modula - tor time register (irmt) to determine whether the carrier or the idle condition is present on irtx. the ir timer is enabled when the ir enable bit (iren) is set to 1. the ir value register (irv) defines the begin - ning value for the carrier modulator. during transmission, the irv register is initially loaded with the irmt value and begins down counting towards 0000h, whereas in receive mode it counts upward from the initial irv register value. during the receive operation, the irv register can be configured to reload with 0000h when capture occurs on detection of selected edges or can be allowed to continue free-running throughout the receive operation. an overflow occurs when the ir timer value rolls over from 0ffffh to 0000h. the ir overflow flag (irov) is set to 1 and an interrupt is generated if enabled (irie = 1). carrier generation module the ircah byte defines the carrier high time in terms of the number of ir input clocks, whereas the ircal byte defines the carrier low time. ? ir input clock (f irclk ) = f sys /2 irdiv[1:0] ? carrier frequency (f carrier ) = f irclk /(ircah + ircal + 2) ? carrier high time = ircah + 1 ? carrier low time = ircal + 1 ? carrier duty cycle = (ircah + 1)/(ircah + ircal + 2) during transmission, the irca register is latched for each irv down-count interval, and is sampled along with the irtxpol and irdata bits at the beginning of each new irv down-count interval so that duty-cycle variation and frequency shifting is possible from one interval to the next, which is illustrated in figure 1. figure 2 illustrates the basic carrier generation and its path to the irtx output pin. the ir transmit polarity bit (irtxpol) defines the starting/idle state and the carrier polarity of the irtx pin when the ir timer is enabled. ir transmission during ir transmission (irmode = 1), the carrier gen - erator creates the appropriate carrier waveform, while the carrier modulator performs the modulation. the car - rier modulation can be performed as a function of carrier cycles or irclk cycles dependent on the setting of the ircfme bit. when ircfme = 0, the irv down counter is clocked by the carrier frequency and thus the modula - tion is a function of carrier cycles. when ircfme = 1, the irv down counter is clocked by irclk, allowing carrier modulation timing with irclk resolution. the irtxpol bit defines the starting/idle state as well as the carrier polarity for the irtx pin. if irtxpol = 1, the irtx pin is set to a logic-high when the ir timer module is enabled. if irtxpol = 0, the irtx pin is set to a logic-low when the ir timer is enabled. a separate register bit, ir data (irdata), is used to determine whether the carrier generator output is output to the irtx pin for the next irmt carrier cycles. when irdata = 1, the carrier waveform (or inversion of this waveform if irtxpol = 1) is output on the irtx pin dur - ing the next irmt cycles. when irdata = 0, the idle condition, as defined by irtxpol, is output on the irtx pin during the next irmt cycles. the ir timer acts as a down counter in transmit mode. an ir transmission starts when the iren bit is set to 1 when irmode = 1; when the irmode bit is set to 1 when iren = 1; or when iren and irmode are both set to 1 in the same instruction. the irmt and irca registers, along with the irdata and irtxpol bits, are sampled at the beginning of the transmit process and every time the ir timer value reload its value. when the irv reaches 0000h value, on the next carrier clock, it does the following: 1) reloads irv with irmt. 2) samples irca, irdata, and irtxpol. 3) generates irtx accordingly. 4) sets irif to 1. 5) generates an interrupt to the cpu if enabled (irie = 1). to terminate the current transmission, the user can switch to receive mode (irmode = 0) or clear iren to 0. carrier modulation time = irmt + 1 carrier cycles
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 15 figure 1. ir transmit frequency shifting example (ircfme = 0) figure 2. ir transmit carrier generation and carrier modulator control carrier output (irv) irdata ir interrupt 0 1 irmt = 3 0 irtx irtxpol = 1 irtx irtxpol = 0 irca irmt irmt = 5 irca = 0202h irca = 0002h irca, irmt, irdata sampled at end of irv down-count interval 3 1 2 0 5 4 3 2 1 0 1 0 0 1 sample irdata on irv = 0000h carrier modulation carrier generation carrier irclk ircfme ircal + 1 ircah + 1 irdata irmt irtxpol irtx pin ir interrupt
16-bit microcontroller with infrared module maxq61c 16 _____________________________________________________________________________________ figure 4. external irtxm (modulator) output figure 3. ir transmission waveform (ircfme = 0) ir transmitindependent external carrier and modulator outputs the normal transmit mode modulates the carrier based upon the irdata bit. however, the user has the option to input the modulator (envelope) on an external pin if desired. if the irenv[1:0] bits are configured to 01b or 10b, the modulator/envelope is output to the irtxm pin. the irdata bit is output directly to the irtxm pin (if irtxpol = 0) on each irv down-count interval bound - ary just as if it were being used to internally modulate the carrier frequency. if irtxpol = 1, the inverse of the irdata bit is output to the irtxm pin on the irv interval down-count boundaries. see figure 4. when the envelope mode is enabled, it is possible to output either the modulated (irenv[1:0] = 01b) or unmodulated (inenv[1:0] = 10b) carrier to the irtx pin. carrier output (irv) irdata ir interrupt irtx irtxpol = 1 irtx irtxpol = 0 0 1 0 irmt = 3 2 3 1 0 2 3 1 0 irdata ir interrupt irv interval irtxm irtxpol = 1 irtxm irtxpol = 0 irmt irmt irmt irmt 0 1 0 1 0 1 0 1
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 17 ir receive when configured in receive mode (irmode = 0), the ir hardware supports the irrx capture function. the irrxsel[1:0] bits define which edge(s) of the irrx pin should trigger the ir timer capture function. the ir module starts operating in the receive mode when irmode = 0 and iren = 1. once started, the ir timer (irv) starts up counting from 0000h when a qualified capture event as defined by irrxsel happens. the irv register is, by default, counting carrier cycles as defined by the irca register. however, the ir carrier frequency detect (ircfme) bit can be set to 1 to allow clocking of the irv register directly with the irclk for finer resolu - tion. when ircfme = 0, the irca defined carrier is counted by irv. when ircfme = 1, the irclk clocks the irv register. on the next qualified event, the ir module does the following: 1) captures the irrx pin state and transfers its value to irdata. if a falling edge occurs, irdata = 0. if a rising edge occurs, irdata = 1. 2) transfers its current irv value to the irmt. 3) resets irv content to 0000h (if irxrl = 1). 4) continues counting again until the next qualified event. if the ir timer value rolls over from 0ffffh to 0000h before a qualified event happens, the ir timer overflow (irov) flag is set to 1 and an interrupt is generated, if enabled. the ir module continues to operate in receive mode until it is stopped by switching into transmit mode (irmode = 1) or clearing iren = 0. carrier burst-count mode a special mode reduces the cpu processing burden when performing ir learning functions. typically, when operating in an ir learning capacity, some number of carrier cycles are examined for frequency determina - tion. once the frequency has been determined, the ir receive function can be reduced to counting the number of carrier pulses in the burst and the duration of the combined mark-space time within the burst. to simplify this process, the receive burst-count mode (as enabled by the rxbcnt bit) can be used. when rxbcnt = 0, the standard ir receive capture functionality is in place. when rxbcnt = 1, the irv capture operation is dis - abled and the interrupt flag associated with the capture no longer denotes a capture. in the carrier burst-count mode, the irmt register only counts qualified edges. the irif interrupt flag (normally used to signal a capture when rxbcnt = 0) now becomes set if two irca cycles elapse without getting a qualified edge. the irif inter - rupt flag thus denotes absence of the carrier and the beginning of a space in the receive signal. when the rxbcnt bit is changed from 0 to 1, the irmt register is set to 0001h. the ircfme bit is still used to define whether the irv register is counting system irclk clocks or irca-defined carrier cycles. the irxrl bit defines whether the irv register is reloaded with 0000h on detection of a qualified edge (per the irxsel[1:0] bits). figure 6 and the descriptive sequence embedded in the figure illustrate the expected usage of the receive burst-count mode. figure 5. ir capture 0 1 0000h irv carrier modulation carrier generation irclk ircfme ircal + 1 ircah + 1 interrupt to cpu irdata irrx pin reset irv to 0000h ir timer overflow ir interrupt irxrl copy irv to irmt on edge detect edge detect
16-bit microcontroller with infrared module maxq61c 18 _____________________________________________________________________________________ 16-bit timers/counters the microcontroller provides two timers/counters that support the following functions: ? 16-bit timer/counter ? 16-bit up/down autoreload ? counter function of external pulse ? 16-bit timer with capture ? 16-bit timer with compare ? input/output enhancements for pulse-width modulation ? set/reset/toggle output state on comparator match ? prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10) figure 6. receive burst-count example 1 1 4 5 6 7 8 9 to 2 3 4 6 7 5 8 9 carrier frequency calculation irrx irv irmt irmt = pulse counting irmt = pulse counting irv = carrier cycle counting capture interrupt (irif = 1). irv irmt. irv = 0 (if irxrl = 1). software sets irca = carrier frequency. software sets rxbcnt = 1 (which clears irmt = 0001 in hardware). software clears ircfme = 0 so that irv counts carrier cycles. irv is reset to 0 on qualified edge detection if irxrl = 1. software adds to irmt the number of pulses used for carrier measurement. irca x 2x counter for space can begin immediately (qualified edge resets). qualified edge detected: irmt++ irv reset to 0 if irxrl = 1. irca x 2 period elapses: irif = 1; carrier absence = space. burst mark = irmt pulses. software clears rxbcnt = 0 so that we capture on the next qualified edge. qualified edge detected: irif = 1, capture irv irmt as the burst space (plus up to one carrier cycle). software set rxbcnt = 1 as in (5). continue (5) to (8) until learning space exceeds some duration. irv rollovers can be used.
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 19 table 2. usart mode details usart the device provides two usart peripherals with the fol - lowing features: ? 2-wire interface ? full-duplex operation for asynchronous data transfers ? half-duplex operation for synchronous data transfers ? programmable interrupt when transmit or receive data operation completes ? independent programmable baud-rate generator ? optional 9th bit parity support ? start/stop bit support serial peripheral interface (spi) the integrated spi provides an independent serial communication channel that communicates synchro - nously with peripheral devices in a multiple master or multiple slave system. the interface allows access to a 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. collision detection is provided when two or more masters attempt a data transfer at the same time. the maximum spi master transfer rate is sysclk/2. when operating as an spi slave, the device can support up to sysclk/4 spi transfer rate. data is transferred as an 8-bit or 16-bit value, msb first. in addition, the spi module supports configuration of an active ssel state (active low or active high) through the slave active select. figure 7. spi master communication timing mode type start bits data bits stop bits mode 0 synchronous n/a 8 n/a mode 1 asynchronous 1 8 1 mode 2 asynchronous 1 8 + 1 1 mode 3 asynchronous 1 8 + 1 1 ssel sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 mosi miso lsb lsb shift sample shift sample t mck t mch t moh t mis t mov t rf t mlh t mih t mcl msb msb-1 msb msb-1
16-bit microcontroller with infrared module maxq61c 20 _____________________________________________________________________________________ general-purpose i/o the microcontroller provides port pins for general-pur - pose i/o that have the following features: ? cmos output drivers ? schmitt trigger inputs ? optional weak pullup to v dd when operating in input mode while the microcontroller is in a reset state, all port pins become high impedance with both weak pullups and input buffers disabled, unless otherwise noted. from a software perspective, each port appears as a group of peripheral registers with unique addresses. special function pins can also be used as general-pur - pose i/o pins when the special functions are disabled. for a detailed description of the special functions avail - able for each pin, refer to the maxq610 users guide . on-chip oscillator an external quartz crystal or a ceramic resonator can be connected between hfxin and hfxout, as illustrated in figure 9. noise at hfxin and hfxout can adversely affect on- chip clock timing. it is good design practice to place the crystal and capacitors near the oscillator circuitry and connect hfxin and hfxout to ground with a direct short trace. the typical values of external capacitors vary with the type of crystal to be used and should be initially selected based on load capacitance as suggested by the manufacturer. figure 8. spi slave communication timing figure 9. on-chip oscillator v dd hfxin clock circuit r f = 1mi q50% c1 = c2 = 12pf stop hfxout c2 c1 r f shift sample shift sample ssel sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 mosi miso t sse t sck t sch t scl t sis t sov t slh t ssh t sd t rf t sih msb msb-1 msb msb-1 lsb lsb
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 21 operating modes the lowest power mode of operation is stop mode. in this mode, cpu state and memories are preserved, but the cpu is not actively running. wake-up sources include external i/o interrupts, the power-fail warning interrupt, wake-up timer, or a power-fail reset. any time the micro - controller is in a state where code does not need to be executed, the user software can put the device into stop mode. the nanopower ring oscillator is an internal ultra- low-power (400na) 8khz ring oscillator that can be used to drive a wake-up timer that exits stop mode. the wake- up timer is programmable by software in steps of 125 f s up to approximately 8s. the power-fail monitor is always on during normal opera - tion. however, it can be selectively disabled during stop mode to minimize power consumption. this feature is enabled using the power-fail monitor disable (pfd) bit in the pwcn register. the reset default state for the pfd bit is 1, which disables the power-fail monitor function during stop mode. if power-fail monitoring is disabled (pfd = 1) during stop mode, the circuitry responsible for generating a power-fail warning or reset is shut down and neither condition is detected. thus, the v dd < v rst condition does not invoke a reset state. power-fail detection figures 10, 11, and 12 show the power-fail detection and response during normal and stop-mode operation. if a reset is caused by a power-fail, the power-fail monitor can be set to one of the following intervals: ? always oncontinuous monitoring ? 2 11 nanopower ring oscillator clocks (~256ms) ? 2 12 nanopower ring oscillator clocks (~512ms) ? 2 13 nanopower ring oscillator clocks (~1.024s) in the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two nanopower ring-oscillator cycles. if v dd > v rst during detection, v dd is monitored for an additional nanopower ring-oscillator period. if v dd remains above v rst for the third nanopower ring period, the cpu exits the reset state and resumes normal operation from utility rom at 8000h after satisfying the crystal warmup period. if a reset is generated by any other event, such as the reset pin being driven low externally or the watchdog timer, the power-fail, internal regulator, and crystal remain on during the cpu reset. in these cases, the cpu exits the reset state in less than 20 crystal cycles after the reset source is removed. figure 10. power-fail detection during normal operation a b c d f g h i e v dd v pfw v rst v por internal reset (active high) t < t pfw t t pfw t t pfw t t pfw
16-bit microcontroller with infrared module maxq61c 22 _____________________________________________________________________________________ table 3. power-fail detection states during normal operation state power-fail internal regulator crystal oscillator sram retention comments a on off off v dd < v por . b on on on v por < v dd < v rst . crystal warmup time, t xtal_rdy . cpu held in reset. c on on on v dd > v rst . cpu normal operation. d on on on power drop too short. power-fail not detected. e on on on v rst < v dd < v pfw . pfi is set when v rst < v dd < v pfw and maintains this state for at least t pfw , at which time a power-fail interrupt is gener - ated (if enabled). cpu continues normal operation. f on (periodically) off off yes v por < v dd < v rst . power-fail detected. cpu goes into reset. power-fail monitor turns on periodically. g on on on v dd > v rst . crystal warmup time, t xtal_rdy . cpu resumes normal operation from 8000h. h on (periodically) off off yes v por < v dd < v rst . power-fail detected. cpu goes into reset. power-fail monitor turns on periodically. i off off off v dd < v por . device held in reset. no operation allowed.
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 23 table 4. stop mode power-fail detection states with power-fail monitor enabled figure 11. stop mode power-fail detection states with power-fail monitor enabled v pfw v rst v por a b c d e f v dd t < t pfw t t pfw t t pfw stop internal reset (active high) state power-fail internal regulator crystal oscillator sram retention comments a on off off yes application enters stop mode. v dd > v rst . cpu in stop mode. b on off off yes power drop too short. power-fail not detected. c on on on yes v rst < v dd < v pfw . power-fail warning detected. turn on regulator and crystal. crystal warmup time, t xtal_rdy . exit stop mode. d on off off yes application enters stop mode. v dd > v rst . cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst . power-fail detected. cpu goes into reset. power-fail monitor turns on periodically. f off off off v dd < v por . device held in reset. no operation allowed.
16-bit microcontroller with infrared module maxq61c 24 _____________________________________________________________________________________ figure 12. stop mode power-fail detection with power-fail monitor disabled table 5. stop mode power-fail detection states with power-fail monitor disabled v pfw v rst v por v dd a b c d e f stop interrupt internal reset (active high) state power-fail internal regulator crystal oscillator sram retention comments a off off off yes application enters stop mode. v dd > v rst . cpu in stop mode. b off off off yes v dd < v pfw . power-fail not detected because power-fail monitor is disabled. c on on on yes v rst < v dd < v pfw . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power-fail warning, and sets the power-fail interrupt flag. turn on regulator and crystal. crystal warmup time, t xtal_rdy . on stop mode exit, cpu vectors to the higher priority of power-fail and the inter - rupt that causes stop mode exit.
16-bit microcontroller with infrared module maxq61c ______________________________________________________________________________________ 25 applications information the low-power, high-performance risc architecture of this device makes it an excellent fit for many portable or battery-powered applications. it is ideally suited for applications such as universal remote controls that require the cost-effective integration of ir transmit/ receive capability. grounds and bypassing careful pcb layout significantly minimizes system-level digital noise that could interact with the microcontroller or peripheral components. the use of multilayer boards is essential to allow the use of dedicated power planes. the area under any digital components should be a con - tinuous ground plane if possible. keep bypass capacitor leads short for best noise rejection and place the capaci - tors as close to the leads of the devices as possible. cmos design guidelines for any semiconductor require that no pin be taken above v dd or below gnd. violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (uninten - tional modification of memory contents). voltage spikes above or below the devices absolute maximum ratings can potentially cause a devastating ic latchup. microcontrollers commonly experience negative volt - age spikes through either their power pins or general- purpose i/o pins. negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. devices such as keypads can conduct electrostatic discharges directly into the micro - controller and seriously damage the device. system designers must protect components against these tran - sients that can corrupt system memory. additional documentation designers must have the following documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and elec - trical specifications. errata sheets contain deviations from published specifications. the users guides offer detailed information about device features and opera - tion. the following documents can be downloaded from www.maxim-ic.com/microcontrollers . ? this maxq61c data sheet, which contains electrical/ timing specifications, pin descriptions, and package information. ? the maxq61c revision-specific errata sheet ( www.maxim- ic.com/errata ). ? the maxq610 users guide , which contains detailed information on features and operation, including pro - gramming. table 5. stop mode power-fail detection states with power-fail monitor disabled (continued) state power-fail internal regulator crystal oscillator sram retention comments d off off off yes application enters stop mode. v dd > v rst . cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power-fail, and puts cpu in reset. power-fail monitor is turned on periodically. f off off off v dd < v por . device held in reset. no operation allowed.
16-bit microcontroller with infrared module maxq61c 26 _____________________________________________________________________________________ deviations from the maxq610 users guide for the maxq61c the maxq610 users guide contains all the informa - tion that is needed to develop application code for the maxq61c microcontroller. however, even though the maxq610 and the maxq61c are largely code-com - patible, there are certain differences between the two devices that must be kept in mind when referring to the maxq610 users guide . ? the maxq61c is a rom-only microcontroller, unlike the maxq610, which contains programmable flash program memory. therefore, all sections in the maxq610 users guide relating to the flash controller, the jtag bootloader, and the debug engine should be disregarded. ? the following registers on the maxq610 (which are described in the maxq610 users guide ) do not exist on the maxq61c, and all references to them should be disregarded: ? port 4 output register (po4) ? port 4 direction register (pd4) ? port 4 input register (pi4) development and technical support maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: ? compilers ? in-circuit emulators ? integrated development environments (ides) ? serial-to-jtag and usb-to-jtag interface boards for programming and debugging (for microcontrollers with rewritable memory) a partial list of development tool vendors can be found at www.maxim-ic.com/maxq_tools . for technical support, go to https://support.maxim-ic. com/micro . package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 32 tqfn-ep t3255+3 21-0140 32 lqfp c32+2 21-0054 44 tqfn-ep t4477+2 21-0144 44 tqfp c44+2 21-0293
16-bit microcontroller with infrared module maxq61c maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 27 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/10 initial release

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